1. Field of the Invention
This invention generally relates to semiconductor devices and methods for fabricating thereof, and more particularly, to a fabricating technique of a non-volatile semiconductor memory device that has improved redundant efficiency of a flash memory of a NOR type.
2. Description of the Related Art
A flash memory, which is a non-volatile semiconductor memory device, has both features of a RAM (Random Access Memory) on which data is rewritable and ROM (Read Only Memory) on which the data is retainable after the power is off. Generally, a smallest memory unit in a memory device is known as cell, and one cell stores one bit. SRAM or DRAM is composed of a single cell made of multiple elements. On the other hand, a single cell in the flash memory is composed of only one transistor, which is a smallest number of the elements. Therefore, it is possible to reduce the cost. The aforementioned single cells are grouped into one sector (block), and a memory region is formed by assembling the aforementioned sectors. Data erase is performed in the memory region on a sector basis (on a chip basis).
The flash memory is categorized into a NAND type and a NOR type. A flash memory of the NAND type includes one data line directly connected by 8-bit or 16-bit of the memory cell, and employs Fowler-Nordheim tunnel effect with the use of whole surfaces of a silicon substrate and a floating gate in both writing and erasing. In contrast, the flash memory of the NOR type includes memory cells respectively connected in parallel to one data line, and utilizes a hot electron in writing and the Fowler-Nordheim tunnel effect in erasing.
FIG. 1 is a schematic cross-sectional view illustrating a connection between the cell in the flash memory of the NOR type and the bit line. A flash memory cell of the NOR type 10 is formed of a semiconductor substrate 11, a floating gate 12, a word line 13, a contact portion 14 (composed of contact holes and conductive members therein), an insulator layer 17, and a bit line 15. The floating gate 12 and the word line 13 are formed inside the insulator layer 17 provided on the semiconductor substrate 11. The contact portion 14 is provided in the insulator layer 17. The bit line 15 establishes contact with the semiconductor substrate 11 (specifically, contact with an impurity diffused layer) through the contact portion 14. With respect to each cell 10 in the flash memory of the NOR type, whether or not the information is stored can be determined by storing an electron in the floating gate 12, the electron having been injected by applying voltage from the word line 13.
In a fabricating process of the cell having the above-mentioned structure, possibly there arises a problem in operation caused resulting from an electric short circuit between the word line 13 and the contact portion 14 due to a defect 16. However, even if a redundancy is applied to the bit line in the problem in operation, the word line 13 still short-circuits the contact portion 14 connected to the bit line 15 to which the redundancy is applied. This prevents the word line 13 from being supplied with sufficient voltage at the time of writing, reading, and erasing the data, and the problem in operation cannot be solved.
This time, even if the redundancy is applied to the word line, only erase operation is performed, yet write operation is not performed on the cell provided on the redundant word line 13 and connected to an irredundant bit line 15. This results in an affect in reading other cells connected to the same bit line 15, because a threshold voltage of the aforementioned cell becomes negative.
FIG. 2 is a view illustrating a circuit configuration of the flash memory of the NOR type. As shown in this figure, one memory cell 10 is connected between the word line 13 and the bit line 15. Any one of the memory cells 10 is conductive, the potential of the bit line 15 decreases.
In FIG. 2, assuming that there is an electric short-circuit between a word line 13-1 and a contact hole provided on a cell 10-1, which is located on an intersection of the word line 13-1 and a bit line 15-1, and then the redundancy is applied to the word line 13-1 and the bit line 15-1 to fix the short-circuiting. The flash memory of the NOR type is erased on a sector (memory block) basis, and accordingly, the erase operation is performed on not only the cell 10-1 but also other cells connected to the redundant word line 13-1 and the redundant bit line 15-1 simultaneously. On the other hand, the write operation is performed on the word line and the bit line selected, the cells connected to the redundant word line 13-1 and the redundant bit line 15-1 cannot be selected and the write operation cannot be performed. Even if the cells connected to the redundant word line 13-1 and the redundant bit line 15-1 can be selected, the sufficient voltage cannot be supplied to the word line and the write operation cannot be performed.
The threshold voltage of the cell, in which only the erase operation is performed and the write operation is not performed, gradually decreases and becomes negative, and then the cell lets a current flow through in a state of the gate voltage of 0 V. On the flash memory of the NOR type, the current flowing through the bit line is detected as a cell current, yet the currents of the cells connected to irredundant bit lines (15-0,15-2, and 15-3) are affected by the cell currents connected to the redundant word line 13-1. This makes it impossible to read the selected cell current properly.
As described above, the redundancy cannot be applied to the problem in operation induced by the electric short-circuit between the word line 13 and the contact portion 14, and the problem cannot be solved.